1. Field of the Invention
The present invention relates to electronic design automation (EDA), and to implementation of layout changes for elements of integrated circuit designs for performance optimization.
2. Description of Related Art
Integrated circuit design is supported by electronic design automation. One approach to EDA supported design is based on the definition of an integrated circuit using a computer system as a netlist of circuit elements. Also, a cell library is provided that includes a number of cells that can be chosen for use in a physical implementation of the circuit elements in the netlist. The cell library has a finite number of choices for the circuit elements, as each cell in the library is pre-qualified for manufacturability and other factors. To implement the netlist, cells are selected from the library, placed in a layout space, and interconnections are defined among the cells. The selection of cells, placement of cells and defining interconnections among the cells can be referred to as placement and routing. The result is a layout file which specifies the shapes and locations of components of the cells, and of the interconnections of the cells which is to be made into an integrated circuit in a foundry.
It has been shown that small layout changes, such as transistor gate length increases, can be used to optimize integrated circuits for performance, leakage power, etc. (See, Clark, et al., “Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design,” In Proc. ISLPED (Newport, Calif., Aug. 9-11, 2004), 274-279).
It is not practical to provide enough choices in a cell library to provide for small layout changes used for these purposes. Also, the optimizations achieved using these small layout changes are often measurable only on analysis of the layout file after placement and routing. However, modern sub-wavelength manufacturing technologies, used to implement the circuits, experience significant optical proximity effects, for which correction is absolutely required. Consequently, in order for layout changes specified by analysis after placement and routing to be realized as intended on an integrated circuit, often times circuit designers need access to the OPC recipe. See, U.S. Pat. No. 7,441,211 by Gupta et al.
Also, there is a very wide range of shape modifications that could be applied based on analysis of a layout file to optimize performance. For example, the drive current and standby leakage current distributions along a transistor's width vary significantly. (See, E. Augendre, et al., “Controlling STI-related parasitic conduction in 90 nm CMOS and below,” ESSDERC, 2002). It is therefore possible to make non-uniform gate shape changes that, for example, achieve significant leakage reduction while sacrificing the drive current only slightly. However, SPICE circuit simulators accept only rectangular gate shapes in order to invoke corresponding device models. The non-uniform shape changes once again will require noticeable custom changes in the OPC recipe.
The need for access to OPC recipes results in practical road blocks to innovation in this technology, because the OPC recipes are foundry process specific, and are usually protected as confidential information by foundries. Interaction between foundries and designers that would be necessary to allow access to the proprietary OPC recipes make these types of small layout changes impractical. This prevents IC optimization from realizing full benefits of these small layout modifications, such as in reduced leakage power.
Problems remain therefore in the realization of practical EDA tools for implementation of small layout changes for design optimization.